An exemplary single layer Metal-oxide-metal (MOM) capacitor structure is shown in FIG. 1A. The structure 100 has periphery metal 102, metal lines 104, and dielectric (oxide) layers 106. To increase the area usage efficiency, multiple layers of MOM capacitor structures could be vertically stacked together. FIG. 1B illustrates a stack (multi-layer) MOM capacitor structure, using vias 112 to connect each layer.
MOM capacitors have been used in the integrated circuits increasingly more often, partly because their minimal capacitive loss to the substrate results in high quality capacitors. Also, MOM capacitors with via have low cost and are easy to implement using a standard logic process. However, conventional MOM capacitors with via tend to have low capacitance and high resistance. Accordingly, important goals in manufacturing MOM capacitors are to increase the capacitance and reduce capacitor resistance, especially for Mixed Signal Radio Frequency (MSRF) product applications. Further, via resistance uniformity and reliable performance are important issues for MOM capacitors with high via density.
Accordingly, new structures and methods for MOM capacitors are desired to achieve higher capacitance and lower resistance, as well as performance reliability.